High-density interconnect (HDI) boards have become essential for modern electronics that demand smaller form factors, faster data rates, and tighter integration. From automotive radar modules and medical imaging systems to high-speed telecom equipment, HDI technology enables dense routing through laser-drilled microvias, fine lines and spaces, and thin laminates. However, as physical dimensions shrink, signal integrity becomes harder to maintain. A trace that works at low speed in a standard PCB can fail completely in an HDI stackup if its characteristic impedance is not calculated accurately. Knowing how to approach impedance calculation for HDI boards helps designers avoid re-spins, reduce signal reflections, and meet the performance targets required by high-speed protocols.
Impedance calculation in HDI boards is not a single formula applied at the end of layout. It is a continuous design process that starts with stackup definition and material selection, continues through trace geometry calculation and simulation, and ends with fabrication and testing. The goal is to create a controlled-impedance environment where each critical signal path remains within the specified impedance tolerance, typically ±10% or tighter for high-speed designs.
Why Impedance Control Is Different in HDI Board Stackups
In a conventional multilayer PCB, controlled impedance is often achieved by adjusting trace width, dielectric thickness, and copper weight within a relatively simple stackup. The distances between signal layers and reference planes are usually large enough to allow wider traces and more forgiving tolerances. HDI boards change this equation significantly. HDI stackups use thin dielectrics, often in the range of 0.05 mm to 0.1 mm per layer, to support laser-drilled microvias and sequential lamination. These thin dielectrics place signal traces much closer to their reference planes, which directly lowers the characteristic impedance for a given trace width.
To maintain a typical 50-ohm single-ended impedance or 100-ohm differential impedance, HDI designers must narrow the trace width substantially. In many HDI designs, controlled-impedance traces fall between 0.075 mm and 0.125 mm wide. This creates a secondary challenge: fine traces are more sensitive to etching variation, copper thickness variation, and surface roughness. A small absolute change in trace width becomes a larger percentage change when the nominal width is very small. As a result, impedance calculations for HDI boards must consider manufacturing tolerances more carefully than standard PCB designs.
Microvias also influence impedance behavior. Because HDI boards use microvias for layer transitions, signals can move between layers with very short via barrels and minimal stubs. This is beneficial for high-speed performance, but it also means that the impedance discontinuity at a via transition must be evaluated in the context of thin dielectrics and dense routing. The via pad, anti-pad, and return-path transitions can introduce capacitive or inductive effects that are more pronounced in compact HDI structures. Accurate impedance calculation therefore extends beyond the trace itself to include the entire signal path, including via transitions, reference plane openings, and component breakout regions.
Material selection adds another layer of complexity. HDI boards frequently use low-loss, high-glass-transition-temperature materials with dielectric constants that vary by resin content, glass style, and frequency. The dielectric constant, often denoted as Dk or εr, is not a single fixed number in real laminates. For thin HDI dielectrics, the effective Dk can differ from the datasheet value due to resin-rich areas, glass weave effects, and copper roughness. Impedance calculation should therefore use the material supplier’s design Dk at the target frequency, not the generic value listed for a standard FR-4 grade. When designers combine high layer counts, thin dielectrics, and mixed material types, a field-solver simulation becomes the most reliable way to predict impedance.
Key Formulas and Parameters for HDI Impedance Calculation
Before calculating impedance, designers need to identify the main physical and electrical parameters. These include the dielectric thickness between the signal trace and its reference plane, the dielectric constant of the laminate, the trace width, the copper thickness, and the trace spacing for differential pairs. In HDI boards, where dielectrics are thin, each parameter has a stronger effect on impedance than it would in a standard PCB. For example, reducing dielectric thickness from 0.1 mm to 0.075 mm can reduce the impedance of a given trace by several ohms unless the trace width is also reduced.
For single-ended microstrip traces on an outer layer, a common approximation for characteristic impedance is:
Z₀ ≈ (87 / √(εr + 1.41)) × ln(5.98 × h / (0.8 × w + t))
In this formula, h is the dielectric height, w is the trace width, and t is the copper thickness. For single-ended stripline traces embedded between two reference planes, a simplified symmetric stripline equation is:
Z₀ ≈ (60 / √(εr)) × ln(4 × h / (0.67 × π × w × (0.8 + t / w)))
These equations provide a useful starting point, but they are approximations. They assume uniform dielectric properties, smooth copper surfaces, and simple geometries. HDI boards often violate these assumptions because of thin prepregs, heavy copper plating, and fine-line etching. The formulas can help designers estimate the required trace width early in the design process, but they should not replace a field-solver simulation for final sign-off.
For differential pairs, impedance calculation becomes more complex because the spacing between the two traces controls the coupling. The differential impedance is approximately twice the odd-mode impedance of one trace. If the two traces are tightly coupled, the odd-mode impedance decreases, so the trace width and spacing must be adjusted together. Common HDI targets include 90-ohm differential impedance for USB and 100-ohm differential impedance for Ethernet, PCIe, and HDMI. In thin HDI stackups, achieving 100-ohm differential impedance may require very narrow traces and small gaps, often in the range of 0.075 mm to 0.1 mm for both width and space.
Because HDI materials and geometries vary widely, the most practical approach is to use a two-dimensional or three-dimensional field solver. A field solver calculates impedance by solving electromagnetic field equations for the exact trace geometry, dielectric stackup, and copper profile. This gives designers a more accurate impedance value and allows quick sensitivity analysis. By adjusting trace width, spacing, and dielectric thickness within the field solver, designers can understand how manufacturing variations will affect impedance before the board reaches fabrication.
Practical Workflow for Calculating and Verifying HDI Impedance
A reliable HDI impedance calculation workflow begins with stackup design. The designer first defines the number of signal layers, power and ground planes, dielectric thicknesses, and material types. For HDI boards, this step is closely tied to the manufacturing process because laser-drilled microvias require specific dielectric thicknesses and copper foil types. The stackup should provide a clear reference plane for each critical signal layer. In dense HDI designs, signals may be routed on multiple build-up layers, so impedance control must be planned for each layer pair individually.
Once the stackup is defined, the next step is to determine the target impedance for each high-speed interface. A single-ended clock or RF signal may require 50 ohms, while a differential pair for PCIe, USB, or Ethernet may require 90 or 100 ohms. The designer then uses an approximation formula or an online impedance calculator to estimate the initial trace width. For HDI boards, this initial value is often much narrower than a standard PCB trace. The calculation should use the design Dk recommended by the material supplier and include the actual copper thickness after plating.
After the initial estimate, the design moves into a field-solver simulation. The field solver models the actual trace geometry, dielectric stackup, copper roughness, and soldermask effects. Designers should run sensitivity analyses to verify that impedance remains within tolerance even if trace width changes by ±10% or dielectric thickness varies by ±5%. This is especially important in HDI boards because fine traces are highly sensitive to process variation. For a more detailed technical walkthrough of each variable, refer to this guide on How to Calculate Impedance for HDI Boards.
Consider a practical example: an automotive telematics module uses a six-layer HDI board with a 0.1 mm dielectric between the outer signal layer and its reference plane. The target is 100-ohm differential impedance for an Ethernet pair. Using a field solver, the designer finds that a trace width of 0.09 mm and a trace spacing of 0.1 mm produce the correct differential impedance. If the fabricator’s etching tolerance is ±0.02 mm, the simulated impedance range remains within ±8%, which may be acceptable for the application. The design can then proceed with a grounded coplanar or broadside-coupled configuration if space is extremely tight.
Finally, impedance calculation should not stop at simulation. It must be verified on the physical board. Fabricators typically build impedance test coupons on the panel using the same stackup and trace geometry as the production board. These coupons are measured with a time-domain reflectometer, or TDR, to confirm that the actual impedance falls within the specified tolerance. For HDI boards, testing is particularly important because thin dielectrics, fine traces, and sequential lamination create more opportunity for impedance drift. By combining careful stackup design, accurate simulation, and physical verification, designers can confidently route high-speed signals through dense HDI boards without sacrificing signal integrity.
